Traffic light controller using Finite state machine with VHDL

The objective of traffic light control system is  to control the flow of vehicles to avoid the traffic jam.
The basic idea behind the project is work with four lane.Further it can be extended for 8 lane system.
The four lanes are east,west,north and south direction.The traffic moving activity is controlled by RED,GREEN,YELLOW signals.

When traffic is moving from west to east then it may move from west to east or west to south where intersection is there, hence control is required. To move from west to north there is no intersection hence a control is not required for that. Similarly when traffic is moving from east to west, then it may also go to east to north, because there is an intersection, but it can go through east to south smoothly without traffic indication. Same rule follows for north to south and south to north vice versa.

Based on above assumption following will be Traffic light state.

STATE	EAST-WEST	NORTH-SOUTH	COUNTER
0	GREEN	RED	120
1	YELLOW	RED	5
2	RED	RED	60
3	RED	GREEN	120
4	RED	YELLOW	5
5	RED	RED	60

BLOCK DIAGRAM:

VHDL Programme:

1) Counter program which can count upto 120 count.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cntr_120is

    Port ( clk : in  STD_LOGIC;

reset : in  STD_LOGIC;

           ce_120 : in  STD_LOGIC;

           co_120_out : out  STD_LOGIC_vector(6 downto 0);

           co_120 : out  STD_LOGIC);

end cntr_120;

architecture Behavioral of cntr_120 is

signal cnt120 : std_logic_vector(6 downto 0);

begin

process(clk,reset,  cnt120)

begin

if (reset = '1') then

  cnt120 <= (others => '0');

elsif(clk'event and clk = '1') then

if (ce_120 = '1') then

  

if (cnt120 = "1111000" ) then

     co_120 <= '1';

     cnt120<=(others=>'0');

else

 cnt120<= cnt120 + 1;

 co_120 <= '0';

end if;

end if;

co_120_out<=  cnt120;

end if;

end process;

end Behavioral;

2) Counter program which can count upto 60 count.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cntr_60 is

    Port ( clk : in  STD_LOGIC;

reset : in  STD_LOGIC;

           ce_60 : in  STD_LOGIC;

           co_60_out : out  STD_LOGIC_vector(6 downto 0);

           co_60 : out  STD_LOGIC);

end cntr_60;

architecture Behavioral of cntr_60 is

signal cnt60 : std_logic_vector(5 downto 0);

begin

process(clk,reset,  cnt60)

begin

if (reset = '1') then

   cnt60 <= (others => '0');

elsif(clk'event and clk = '1') then

if (ce_60 = '1') then

   

if (cnt60 = "111100" ) then

      co_60 <= '1';

      cnt60<=(others=>'0');

else

  cnt60<= cnt60 + 1;

  co_60 <= '0';

end if;

end if;

co_60_out<=  cnt60;

end if;

end process;

end Behavioral;

3) Counter program which can count upto 5 count.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cntr_5 is

    Port ( clk : in  STD_LOGIC;

reset : in  STD_LOGIC;

           ce_5 : in  STD_LOGIC;

           co_5_out : out  STD_LOGIC_vector(2 downto 0);

           co_5 : out  STD_LOGIC);

end cntr_5;

architecture Behavioral of cntr_5 is

signal cnt5 : std_logic_vector(2 downto 0);

begin

process(clk,reset,  cnt5)

begin

if (reset = '1') then

   cnt5 <= (others => '0');

elsif(clk'event and clk = '1') then

if (ce_5 = '1') then

   

if (cnt5= "101" ) then

      co_5 <= '1';

      cnt5<=(others=>'0');

else

  cnt5<= cnt5 + 1;

  co_5 <= '0';

end if;

end if;

co_60_out<=  cnt60;

end if;

end process;

end Behavioral;