Compilation and Simulation of VHDL Code
Compiler (Analyzer) –
checks the VHDL source code
·
Does it conforms with VHDL syntax and semantic rules
·
Are references to libraries correct
Intermediate
form used by a simulator or by a synthesizer Elaboration
create ports, allocate memory storage,
create interconnections, establish mechanism for executing of VHDL process.
Transactions and Events
We need to analyse a sub module only when its
inputs change. The change in the value of a signal is called an “event”.
Whenever
an event occurs at the input, we re-evaluate the output(s). However, the
output(s) will not change immediately. Depending on the delay, we make a note
of the time in future when the newly calculated values for the output(s) should
appear.
Each
one of these is called a “transaction”.
Note
that when the time comes for the output to acquire this value, it may or may
not result in an event. (For example, an AND gate may have one of its inputs at
0 and the other input may experiences an event. The recalculated output will
remain the same – i.e. 0.
Thus there is no change in its value
and hence, no event.)
If it
does cause an event, we must re-calculate the outputs of all those sub modules
for which this output signal is an input. And so on……..
Timing “Delta”
The
delay in the output acquiring its calculated value can be made zero, if
desired. However, we assume that the output appears after a time d and then
take the limit as d→0.
This
has scheduling consequences. (Events occurring at T+d are handled before those
occurring at T+2d, even though both appear to be simultaneous if d→0).
Types of Delay
Consider an RC delay
followed by a buffer. A pulse
much wider than the RC time will be replicated at the output after some delay.
A pulse much narrower than the RC time
will vanish. If the same amount
of delay is caused by an optical fibre, both the narrow and the wide pulse will
appear at the output after being delayed. The amount of delay is the same, but their type is different and must be
modeled differently.
Delay Types in VHDL
All VHDL signal assignment statements
prescribe an amount of time that must transpire before the signal assumes its
new value
This
prescribed delay can be in one of three forms:
Transport -- prescribes
propagation delay only
Inertial --
prescribes propagation delay and minimum input pulse width
Delta -- the default if no
delay time is explicitly specified
We call the two types of
delay as “inertial” and “transport” type.
Inertial
delay is by far the most common type encountered in electronic circuits.
Transport
delay can be useful in behavioural descriptions. For example, a shift register
based delay line can be modelled as transport delay. Delta delay
is used in VHDL for queuing up sequential events. The time between the two
sequential events is called delta delay. Delta delay
has no equivalent in real time. In a signal assignment the
value is not assigned to the signal directly but after a delta delay at the
earliest. Default signal assignment propagation delay if no delay is explicitly
prescribed Delta is an infinitesimal VHDL time unit so that
all signal assignments can result in signals assuming their values at a future
time
Example:
Output
<= NOT Input;
--
Output assumes new value in one delta cycle
supports a model of concurrent VHDL
process execution order in which
processes are executed by simulator does not affect simulation output
Example.
B<=a;
Here
signal b is assigned a value of signal a after one delta delay.( Reference for
a simulator and not seen in real time).
C<= a and b;
D<=not c;
In the above example:
‘a’ and ‘b’ are evaluated and
assigned to ‘c’ after 1delta delay time as shown in the wave form.
Inverted
value of ‘c’ assigned after 2 delta delays as shown in the wave form.
But
these delays we won’t be able to observe on the simulator.
Inertial Delay
Provides
for specification propagation delay and input pulse width, i.e. ‘inertia’ of
output:
target <=
[REJECT time_expression] INERTIAL waveform
Inertial
delay is default and REJECT is optional
Output
<= NOT Input AFTER 10 ns;
--
Propagation delay and minimum pulse width are 10ns
Example
of gate with ‘inertia’ smaller than propagation delay
Example: Inverter with propagation delay of 10ns which
suppresses pulses shorter than 5ns
Output <= REJECT 5ns INERTIAL NOT
Input AFTER 10ns;
Inertial
delay is the default delay in VHDL. Inertial delay the values appears at the
output only when specified time the input is stable.
If
the input is not stable for specified limit no output change occur.
Example:
Z<= not A after 10 ns;
OR
Z<= not A inertial after
10 ns;
VHDL-87 Inertial delay model
Any input
signal change that does not persist for at least a propagation delay of the
device is not reflected at the output.
Inertial
delay (pulse rejection limit) = propagation delay
VHDL-93
Enhanced inertial delay model
VHDL-93
allows the inertial delay model to be declared explicitly as well as implicitly.
Explicitly:
Z_OUT <=
inertial
(not A_IN and B_IN and C_IN) or
(A_IN and not B_IN and C_IN) or
(A_IN and B_IN and not C_IN) or
(A_IN and B_IN and C_IN) after 20 ns;
Implicitly:
Z_OUT <=
(not A_IN and B_IN and C_IN) or
(A_IN and not B_IN and C_IN) or
(A_IN and B_IN and not C_IN) or
(A_IN and B_IN and C_IN) after 20 ns;
VHDL-93 Enhanced inertial delay model
VHDL-93
allows inertial delay, also called a pulse
rejection limit, to be different from the
propagation delay.
SIG_OUT <= reject 5 ns inertial not SIG_IN
after 7 ns;
Transport delay:
With a transport delay model, all input signal changes are reflected at the
output, regardless of how long the signal changes
persist. Transport delay model must be declared explicitly using the keyword transport.
Inertial delay model is a default delay model
because it reflects better
the actual behaviour of logic components.
Transport delay model is used for high-level modelling. Transport delay transports any changes on an
input to the output after the specified time.
Example:
Z<= transport not A after 10 ns;
In the previous slide the output ‘Z’ assigned the
inverted value of ‘A’ after 10 ns;
Here the any changes on an input will be transported
to the output after the specified time
10 ns.
•Routing delays are modelled using
transport delay.
